Project 38: Research in the Next Generation of DFM Physical Design Modeling, Verification, and Optimization Algorithm Based on Deep Learning Techniques
Contact Information:
Assoc. Prof. Yongfu Li
Email: yongfu.li@sjtu.edu.cn
Project Description and Objectives:
With the increasing demand for more integrated circuit chips, ranging from automotive vehicles, computers/servers, and mobile devices, it has been reported that the cost of producing new cutting-edge chips with the latest technology is now more than $500 million. To lower the financial barriers of designing chips, reducing the design cycle and increasing design robustness, it is important to have a comprehensive circuit verification and optimization tools. In this research internship program, we aim to cultivate the next generation of EDA software engineers through the development of machine/deep learning-based EDA software. The researcher will be involved in one of the existing research projects and assist the post-graduate researchers in their work. One example of our current research is based on using deep learning technology to develop new pattern-matching software to detect all the outlier polygon shapes in a layout that prevents any catastrophic failures in the chip. The intern will need to have a basic understanding of the CMOS process, deep learning techniques, and Python programming language. The intern will explore different deep learning models and hyper-parameters optimization to identify the best model for physical verification.
Eligibility Requirements:
Proficiency in English writing and speaking is mandatory.
Basic knowledge of machine learning, semiconductor, and circuit design.
Programming skills on Unix operating system and Python programming.
Main Tasks:
Develop a prototype software.
Finish a report of the internship.
Give two research presentations (a. references review; b. technical presentation).
Submit one paper to a journal.
Website:
School: http://english.seiee.sjtu.edu.cn/