ECE4270J VLSI Design I

ECE4270J VLSI Design I

Number of Credits

4

Teaching Hours

58

Offering School

UM-SJTU Joint Institute

Course Teacher

Xuyang Lu 

Course Level

Undergraduate Level

Language of Instruction

English

First Day of Class

May 2023 (TBD)

Last Day of Class

Aug 2023 (TBD)

Course Component

Lecture

Mode of Teaching

Synchronous

Meeting Time

TBD

Every Monday and Wednesday from 14:00 pm - 15:40 pm, and 16:00 pm - 17:40 pm on Friday at even weeks, 13 weeks in total.

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Time Zone

Beijing Time(UTC+8)

Course-specific Restrictions (e.g. Prerequisites / Major / Year of Study)

For 3rd/4th year undergraduate students

Course Description

This course is primarily designed for senior undergraduate students interested in integrated circuit design. We will cover the fundamentals and the tools for designing a real-life system. Students are expected to learn digital circuit design and get familiar with design tools including cadence and Synopsys.

Syllabus

English

This course is available on APRU-VSE platform.